1. Field of the Invention
The invention generally relates to synchronizers. More particularly, the present invention relates to advanced high performance bus (AHB) synchronizer designs.
2. Background Art
Conventional synchronizer designs provide solutions for transferring data from one clock domain to another clock domain where the two clock domains have a 1:N synchronized or a totally unsynchronized relationship. These solutions, however, cannot accommodate systems where the clocks have an N:M relationship. Furthermore, these conventional systems do not preserve burst operations or burst operations are blindly preserved without optimizing system performance.
What is needed therefore, is an advanced high performance bus (AHB) design capable of transferring data from one clock domain to another clock domain independent of the relationship of the domain clocks. More specifically, what is needed is an AHB synchronizer design capable of preserving the burst while transferring data from one clock domain to another clock domain where the associated clocks have an N:M relationship. Such a synchronizer design is desirably configurable for either minimum latency or maximum throughput mode.